(China (Mainland))
Product Summary
The MT49H16M36HU-33:A is a reduced latency DRAM. The Micron 256Mb Reduced Latency DRAM (RLDRAM) contains 8 banks x32Mb of memory accessible with 32-bit or 16-bit I/Os in a double data rate (DDR) format where the data is provided and synchronized with a differential echo clock signal. The MT49H16M36HU-33:A does not require row/column address multiplexing and is optimized for fast random access and high-speed bandwidth. The MT49H16M36HU-25:A is designed for communication data storages like transmit or receive buffers in telecommunication systems as well as data or instruction cache applications requiring large amounts of memory.
Parametrics
MT49H16M36HU-25E:A absolute maximum ratings: (1)Storage Temperature: -55℃ to +150℃; (2)I/O Voltage: -0.3V to + VDDQ + 0.3V; (3)Voltage on VEXT Supply Relative to VSS: -0.3V to +2.8V; (4)Voltage on VDD Supply Relative to VSS: -0.3V to +2.1V; (5)Voltage on VDDQ Supply Relative to VSS: -0.3V to +2.1V; (6)Junction Temperature: 100℃.
Features
MT49H16M36HU-25E:A features: (1)2.5V VEXT, 1.8V VDD, 1.8V VDDQ I/O; (2)Cyclic bank addressing for maximum data out bandwidth; (3)Non-multiplexed addresses; (4)Non-interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch) DDR; (5)Target 600 Mb/s/p data rate; (6)Programmable Read Latency (RL) of 5-8; (7)Data valid signal (DVLD) activated as read data is available; (8)Data Mask signals (DM0/DM1) to mask first and second part of write data burst; (9)IEEE 1149.1 compliant JTAG boundary scan; (10)Pseudo-HSTL 1.8V I/O Supply; (11)Internal Auto Precharge; (12)Refresh requirements: 32ms at 100℃ junction temperature (8K refresh for each bank, 64K refresh command must be issued in total each 32ms).
Diagrams
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Negotiable |
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MT49H8M36FM-25 TR |
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Negotiable |
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